EP4SGX360NF45I4N 920 I/O 600MHz Stratix IV FPGA

■ Thirty-two out of the 48 transceiver channels have dedicated physical coding sublayer (PCS) and physical medium attachment (PMA) circuitry and support
data rates between 600 Mbps and 8.5 Gbps
■ The remaining 16 transceiver channels have dedicated PMA-only circuitry and support data rates between 600 Mbps and 6.5 Gbp
■ Stratix IV GX—PCIe Gen1 and Gen2, GbE, Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, GPON,
SAS/SATA, HyperTransport 1.0 and 3.0, and Interlaken
■ Root complex and end-point applications
■ x1, x4, and x8 lane configurations
■ PIPE 2.0-compliant interface
■ Embedded circuitry to switch between Gen1 and Gen2 data rates
■ Built-in circuitry for electrical idle generation and detection, receiver detect, power state transitions, lane reversal, and polarity inversion
■ 8B/10B encoder and decoder, receiver synchronization state machine, and ± 300 parts per million (ppm) clock compensation circuitry
■ Transaction layer support for up to two virtual channels (VCs)
■ XAUI/HiGig Support
■ Compliant to IEEE802.3ae specification
■ Embedded state machine circuitry to convert XGMII idle code groups (||I||) to and from idle ordered sets (||A||, ||K||, ||R||) at the transmitter and
receiver, respectively
■ 8B/10B encoder and decoder, receiver synchronization state machine, lane deskew, and ± 100 ppm clock compensation circuitry