5SGXMA5K2F40C3N 14.1Gb/S 900mV ALTERA FPGA Chip

• 0.85-V or 0.9-V core voltage
• 28.05-Gbps transceivers on Stratix V GT devices
• Electronic dispersion compensation (EDC) for XFP, SFP+, QSFP, CFP optical module support
• Adaptive linear and decision feedback equalization
• Transmitter pre-emphasis and de-emphasis
• Dynamic reconfiguration of individual channels
• On-chip instrumentation (EyeQ non-intrusive data eye monitoring)
• 600-Megabits per second (Mbps) to 12.5-Gbps data rate capability
• 1.6-Gbps LVDS
• 1,066-MHz external memory interface
• On-chip termination (OCT)
• 1.2-V to 3.3-V interfacing for all Stratix V devices
• PCIe Gen3, Gen2, and Gen1 complete protocol stack, x1/x2/x4/x8 end point and root port
• Interlaken physical coding sublayer (PCS)
• Gigabit Ethernet (GbE) and XAUI PCS
• 10G Ethernet PCS
• Serial RapidIO® (SRIO) PCS
• Common Public Radio Interface (CPRI) PCS
• Gigabit Passive Optical Networking (GPON) PCS
• Programmable Power Technology
• Quartus II integrated PowerPlay Power Analysis